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| Ordering number : EN4469A Monolithic Linear IC LA4805V 3 V Stereo Headphone Power Amplifier Overview The LA4805V is a power IC developed for use in stereo headphones. It includes low frequency enhancement, beep function and output control circuits on-chip. Furthermore, the LA4805V realizes a high S/N ratio, a high ripple exclusion ratio, and low current drain. Package Dimensions unit: mm 3191-SSOP30 [LA4805V] Functions * * * * * * Stereo headphone power amplifier Low frequency enhancement (L.BOOST) Beep amplifier Output suppression circuit (PVSS) Power switch Muting switch Features * * * * * Low current drain (8.3 mA typical) High S/N ratio (90 dB typical, 13 V) High ripple exclusion ratio (75 dB typical) No output electrolytic capacitors required Ultra-miniature package (SSOP-30) SANYO: SSOP30 Specifications Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Conditions Ratings 4.5 500 -15 to +50 -40 to +150 Unit V mW C C Operating Conditions at Ta = 25C Parameter Recommended supply voltage Recommended load resistance Operating supply voltage range Symbol VCC RL VCC op Conditions Ratings 3.0 16 to 32 1.8 to 3.6 Unit V V Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O3098HA (OT)/40794TH B8-0242 No. 4469-1/17 LA4805V Operating Characteristics at Ta = 25C, VCC = 3.0 V, f = 1 kHz, 0.775 V = 0 dBm, RL = 10 k (L.B), RL = 16 (PWR) Ratings Parameter [L.BOOST +PVSS + PWR] ICCO1 Quiescent current ICCO2 ICCO3 ICCO4 [PWR AMP] Output power Voltage gain Channel balance Total harmonic distortion Output noise voltage Crosstalk Ripple exclusion ratio Muting attenuation Beep output Output current offset Input resistance [L.BOOST] Voltage gain Boost* Maximum output voltage Total harmonic distortion Crosstalk Output noise voltage Ripple exclusion ratio [L.BOOST + PWR] Voltage gain Output voltage Total harmonic distortion Crosstalk VG3 VO1 THD3 CT3 VIN = -30 dBm, f = 1 kHz, boost on/off VIN = -30 dBm, f = 100 Hz, boost on VIN = -30 dBm, f = 100 Hz, boost on VO = -20 dBm, RV = 0 , boost on VIN = -30 dBm, PVSS2 The input amplitude when the output is +3 dB over the starting point VIN = -40 dBm, PVSS2 PVSS2 -41 25 8 0.13 10 0.23 0.14 32.5 12 0.33 0.5 dB V % dB VG2 L.BTS1 L.BTS2 VO max THD2 CT2 VNO2 SVRR2 VIN = -30 dBm, boost on/off VIN = -30 dBm, f = 100 Hz, boost on VIN = -30 dBm, f = 10 kHz, boost on THD = 1%, boost on VO = 0.1 V, boost on VO = -20 dBm, Rg = 0, boost on Rg = 0, boost off Rg = 0, f = 100 Hz, Vg = -20 dBm, boost on 50 25 -3.2 13 3 0.2 -5.2 15 5 0.4 0.085 30 3 60 10 -7.2 17 7 0.6 0.25 dB dB dB V % dB V dB PO VG1 VBL THD1 VNO1 CT1 SVRR1 ATTM VO BEEP VDC OFF Ri THD = 10% VO = -10 dBm VO = -10 dBm VO = 0.35 V Rg= 0, DIN AUDIO VO = -10 dBm, TUN = 1 kHz, Rg = 0 VCC = 1.8 V, f = 100 Hz, VR = -20 dBm, TUN = 100 Hz THD = 1%, Rg = 0 k VIN = -16 dBm (sine wave) VIN = 0 V, Rg = 0 35 60 80 1.0 -20 7 15 15.7 -1 25 17.7 0 0.1 13 45 75 90 3.0 0 10 20 13 19.7 1 0.3 25 mW dB dB % V dB dB dB mV mV k IC off Muting on Rg = 0, L.BST/PVSS off Rg = 0, L.BST/PVSS on 1.0 4.0 4.5 0.05 2.7 8.3 8.6 1.0 5.0 12.0 12.5 A mA mA mA Symbol Conditions min typ max Unit [L.BOOST + PVSS + PWR]: When VO1 is maximum PVSS voltage PVSS width PVSS distortion PVSS starting input Note: * Boost levels relative to 1 kHz VO PVSS2 VO PVSS W THD PVSS VIN PVSS -32.5 25 -37.5 30 0.55 -46 -42.5 35 2.0 -51 dBm dB % dBm No. 4469-2/17 LA4805V Pin Assignment and Block Diagram No. 4469-3/17 LA4805V Test Circuit No. 4469-4/17 LA4805V Sample Application Circuit No. 4469-5/17 LA4805V Pin Functions and Equivalent Circuits (VCC = 3.0 V) Pin No. Symbol VDC (V) Equivalent circuit Pin function Unit (resistance: ) 1 PWR SW 0 to 0.7 * Applying VCC to pin 1 turns the IC power on. 2 4 IN 2 IN 1 1.1 1.1 * Low boost input pin 3 5 H.P 1 H.P 2 1.1 1.1 * High-pass input pin 6 PRE GND 7 8 MIX OUT 1 MIX OUT 2 1.1 1.1 * Low boost and buffer output pin 9 11 PWR IN 1 PWR IN 2 1.1 1.1 * Power input pin * The input resistance is 10 k. 10 PWR IN C 1.1 * Power amp common input pin * Connect to Vref in normal operation Continued on next page. No. 4469-6/17 LA4805V Continued from preceding page. Pin No. Symbol VDC (V) Equivalent circuit Unit (resistance: , capacitance: F) Pin function 12 VREF OUT 1.1 * Fixed bias of 1.1 V 13 VREF CONT 1.1 * The VREF CONT pin, 1.1 V 14 DET 1 0 to 1.3 * AVLS operates at 0.65 V or higher. 15 Beep IN 1.1 * Beep input pin * Only operates when the muting function is on. 16 R.F CONT 2.2 * The R.F. CONT pin 17 R.F OUT 2.65 * Set to a bias of about 0.88 times VCC. Continued on next page. No. 4469-7/17 LA4805V Continued from preceding page. Pin No. Symbol VDC (V) Equivalent circuit Unit (resistance: , capacitance: F) Pin function 18 PVSS S.C 0 to 0.7 * Smoothing pin used when PVSS is turned on and off. 19 PVSS SW 0 to 1.1 * PVSS is turned on by the power output signal, and turned off when grounded. 20 VCC 21 22 24 PWR OUT 2 PWR OUT C PWR OUT 1 1.1 1.1 1.1 * The power output pins * The LA4805V drives headphones with pin 22 used as a common center. (No electrolytic capacitors are used in the output.) 23 PWR GND 25 LOW BOOST SW 0 to 1.0 * The low boost function is turned on when this pin is floating and turned off when it is connected to Vref. 26 DET 2 0.5 to 1.3 * ALC operates at 0.65 V or higher. 27 L.P 2 1.1 * Low boost secondary low pass pin Continued on next page. No. 4469-8/17 LA4805V Continued from preceding page. Pin No. Symbol VDC (V) Equivalent circuit Pin function Unit (resistance: ) 28 LOW BOOST NF 1.1 * Low boost NF pin 29 L.P 1 1.1 * Low boost primary low pass pin 30 MUTE SW 0 to 2.2 * The muting function is on when this pin is floating and off when connected to VCC through a 100 k resistor. External Component Functions: Recommended values are indicated in parentheses. * C1, C3 (1 to 4.7 F) Input coupling capacitors * C2, C4 (2200 pF) Input high pass capacitors. The high region gain when low boost is on is determined by the IC internal 18 k resistance and these external 2200 pF capacitors. * C5, C6 (0.1 to 1 F) Mixer amplifier to power amplifier coupling capacitors * C7, C8 (3.3 to 10 F) Reference bias (Vref) decoupling capacitors * C9 (10 to 22 F) Determines the PVSS recovery time. * C10 (0.1 to 1 F) Beep input coupling capacitor. Be sure that this capacitor does not attenuate the beep signal. * C11, C12 (4.7 to 10 F) Ripple filter capacitors. Care is required selecting their value, since although increasing the capacitance increases the ripple exclusion ratio, it also increases the rise time when the power is turned on. * C13 (3.3 to 4.7 F) Smoothing capacitor for PVSS on/off switching noise No. 4469-9/17 LA4805V * C14 (0.22 to 0.47 F) Coupling capacitor that accepts the power output signal and inputs that signal to the PVSS function. * C15 (220 F) Power supply line decoupling capacitor * C16, C17, C18 (0.22 to 0.47 F) Oscillation suppression capacitors. We recommend using film capacitors. * C19 (2.2 to 4.7 F) Smoothing capacitor for low boost on/off switching noise * C20 (3.3 to 4.7 F) Determines the low boost attack time. Increasing the capacitance increases the attack time. * C21, C23 (0.1 F) Low pass capacitors used with the low boost function * C22 (2.2 to 4.7 F) Low boost amplifier NF capacitor. Values in excess of the recommended range will slow the low boost amplifier's rise time and may cause noise spikes. * C24 (0.1 to 1.0 F) Determines the muting time. See the "IC Usage Notes" section for a discussion of the muting time when the capacitor C24 value is varied. * R1, R2 (10 k) Mixer amplifier load resistance and power input adjustment potentiometer. * R3 (100 k to 1 M) Smoothing resistor for PVSS on/off switching noise * R4 (50 k to 200 k) PVSS level adjustment resistor * R5, R6, R7 (1 to 4.3 ) Power amplifier oscillation suppression capacitors. We recommend using film capacitors. * R8, R9 (15 k) Power output signal bias resistor for PVSS operation * R10 (20 k) Determines the pin 25 bias when low boost is off. * R11 (1.5 k to 2.2 k) Determines the low boost amplifier's voltage gain. * R12 (100 k) Determines the pin 30 bias when muting is off (and PWR is on). We recommend using a 100 k resistor for R12, since the muting switch pin (pin 30) threshold area is determined by this (100 k) resistance and the IC's internal 300 k resistance. No. 4469-10/17 LA4805V Usage Notes and Operating Principles 1. Beep function operating principles * The figure above shows the beep function block, which is designed to operate when muting is on, i.e., when pin 16 is open. The output voltage generated at RL at that time is given by the following equation. VO = RL x VA RL + 3 k + 1 k 16 x 0.5 V 2 mV 16 + 3 k + 1 k For example, when RL is 16 and VA is 0.5 V: (VA is adjusted by the pin 9 input level.) VO = * While the beep output VO is determined by the formula above, it is influenced by the capacitor and resistor used to form the PWR output oscillation suppression function. Therefore, when using the beep function, it is necessary to make the impedance due to the pin 13 capacitor C10 smaller than the impedance of capacitors C9 and C10 on pins 12 and 15, since pin 13 is a common output. Which is to say, the capacitor C10 must be larger than the capacitors C9 and C10. 2. Muting time * The figure above shows the waveform when the muting function is turned on and off. The ts on and off times here can be changed by the capacitor Cr on pin 16. While the recommended value for Cr is 1 F, note that reducing this value can lead to increased impulse ("pop") noise. No. 4469-11/17 LA4805V * The table below lists the ts on and off times for different values of Cr. Cr 0.1 F 1.0 F 2.2 F ts OFF 15 ms 150 ms 300 ms ts ON 3.2 ms 30 ms 56 ms 3. Boost level when the low boost function and PVSS are on * Normally, the 100 Hz boost level with respect to 1 kHz is 15 dB when low boost is on. However, the LA4805V is designed so that the 100 Hz boost level with respect to 1 kHz is 9 dB when both PVSS and low boost are on. PVSS is turned on when the power output is input to pin 19, and the low boost level is determined by adjusting the DET as shown by the dotted lines in the figure. (See the separately provided detailed data describing the state where both low boost and PVSS are on.) * The graphs below give a simplified view of the fi-VG characteristics. 4. PVSS No. 4469-12/17 LA4805V * As shown in the figure above, PVSS is designed so that PVSS is operated and turned on by inputting to pin 19 the mixed power outputs through 15 k resistors. When this input is grounded, PVSS is turned off. * PVSS switching can be changed by an IC internal 30 k resistor and an external (150 k) resistor. When this function is used, VO is set to 45 mV by passing the mixed signal through a 150 k resistor at PVSS1, and is set to 10 mV by passing the mixed signal through only the 0.22 F capacitor at PVSS2. (Detailed data is provided separately.) * The graph below gives a simplified view of the Vi-VO characteristics and the output VO when RP is varied. RP 50 k 100 k 150 k 200 k VO 25 mV 35 mV 46 mV 56 mV No. 4469-13/17 LA4805V No. 4469-14/17 LA4805V No. 4469-15/17 LA4805V No. 4469-16/17 LA4805V Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 4469-17/17 |
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